Technical Field
The present disclosure relates to integrated circuits and the fabrication thereof. More particularly, the present disclosure relates to fabricating field effect transistors (FETs) that include fins (fin-FETs) while protecting against parasitic capacitance and protecting high K materials of a replacement metal gate structure when building in insulating air gaps.
Description of the Related Art
Multi-gate FETs may experience in high parasitic capacitance. Insulating selected regions of the device may reduce the parasitic capacitance, however, the processing employed to add insulation may harm other device components, such as a high dielectric constant material (high k material) that is part of a replacement metal gate structure, e.g., a gate structure formed in replacement of a sacrificial gate structure. For example, in taking steps to improve the insulating characteristics, processing near the gate may lead to the exposure of and damage to high k material situated around the metal gates.